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A simple reconfigurable microprocessor in a 36 macrocell CPLD

Authors:

W.A.S. Wijesinghe,

Department of Electronics, Faculty of Applied Sciences, Wayamba University of Sri Lanka, Makandura., LK
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M.K. Jayananda,

Centre for Instrument Development, Department of Physics, Faculty of Science, University of Colombo, Colombo 03., LK
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D.U.J. Sonnadara

Centre for Instrument Development, Department of Physics, Faculty of Science, University of Colombo, Colombo 03., LK
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Abstract

This paper describes a simple microprocessor developed using a complex programmable logic device (CPLD), with an instruction set optimized for data acquisition applications. The processor encompasses a tiny instruction set having only the instructions required in data acquisition applications. Due to optimization of the features, it was possible to fit both the CPU and the programme memory in the 36 macrocell Xilinx XC9536XL CPLD. The designing of the CPU was carried out using the hardware description language VHDL. The reconfigurability of the CPLD using VHDL enables the change of features of the CPU, including the instruction set, to suit user requirements. An example data acquisition system implemented using this CPU is also discussed.

Keywords: CPLD, data acquisition, FPGA, microcontrollers, reconfigurable computing, VHDL.

Doi: 10.4038/jnsfsr.v39i3.3630

J.Natn.Sci.Foundation Sri Lanka 2011 39 (3): 261-266

How to Cite: Wijesinghe, W.A.S., Jayananda, M.K. and Sonnadara, D.U.J., 2011. A simple reconfigurable microprocessor in a 36 macrocell CPLD. Journal of the National Science Foundation of Sri Lanka, 39(3), pp.261–266. DOI: http://doi.org/10.4038/jnsfsr.v39i3.3630
Published on 27 Sep 2011.
Peer Reviewed

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