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Research Articles

Simulation of diffusion limited aggregation in field programmable gate arrays

Authors:

W. A. S. Wijesinghe,

Department of Electronics, Faculty of Applied Sciences, Wayamba University of Sri Lanka, Makandura., LK
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M. K. Jayananda,

Department of Physics, Faculty of Science, University of Colombo, Colombo 03., LK
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D. U. J. Sonnadara

Department of Physics, Faculty of Science, University of Colombo, Colombo 03., LK
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Abstract

Abstract: This paper presents design considerations and performance in implementation of Diffusion-limited aggregation (DLA) process on a Xilinx Spartan 3 field programmable gate array (FPGA). The DLA cluster algorithm was implemented as a block RAM and two 32-bit Linear Feedback Shift Register random number generators in hardware. The complete design, written in VHDL and synthesized using Xilinx WebPACK 7.2 was downloaded to the Spartan 3 device for speed measurements. A 300% speed improvement compared to a software based implementation of the same algorithm was observed when the design was tested in a XC3S1000 FPGA operated with a 100 MHz clock.

Keywords: Dedicated hardware, FPGA, Monte Carlo simulation, VHDL, Xilinx.

Doi: 10.4038/jnsfsr.v38i4.2647

J.Natn.Sci.Foundation Sri Lanka 2010 38 (4): 213-218

How to Cite: Wijesinghe, W.A.S., Jayananda, M.K. and Sonnadara, D.U.J., 2010. Simulation of diffusion limited aggregation in field programmable gate arrays. Journal of the National Science Foundation of Sri Lanka, 38(4), pp.213–218. DOI: http://doi.org/10.4038/jnsfsr.v38i4.2647
Published on 30 Dec 2010.
Peer Reviewed

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