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Performance evaluation of multipliers in reconfigurable hardware

Authors:

WAS Wijesinghe,

Department of Electronics, Faculty of Applied Sciences, Wayamba University of Sri Lanka, Mankandura., LK
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MK Jayananda,

Department of Physics, Faculty of Science, University of Colombo, Colombo 03., LK
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DUJ Sonnadara

Department of Physics, Faculty of Science, University of Colombo, Colombo 03., LK
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Abstract

Hardware multiplier is a critical element in many computing intensive sub-systems that are implemented in Field Programmable Gate Arrays (FPGAs). In this study, performance comparison between several different types of array-based unsigned 8-bit multipliers (both combinational and pipelined) for two types of FPGAs (XC4005XLPC84-3C and XC3S1000FT256-4C Spartan 3) in terms of resource utilization and critical path delays was carried out. For combinational multipliers, the embedded multiplier in the high density Spartan 3 FPGA has the lowest critical path delay. MUX-based Carry Save Array (CSA) multiplier when implemented in the low density XC4005 FPGA, utilized 24% less resources and resulted is 42% improvement in the latency than the standard multiplier available in the hardware description language (VHDL) library. For pipelined multipliers, single stage pipelined multiplier of the same architecture, for the same chip, utilized 18% more resources but produced a 84% improvement in the latency. Thus, to obtain the optimum performance of FPGA hardware in high speed applications, MUX-based pipelined CSA multipliers are recommended.

Keywords: FPGA, Multiplier hardware architecture, reconfigurable computing, VHDL  

doi:10.4038/jnsfsr.v36i3.160  

Journal of the National Science Foundation of Sri Lanka 36 (3) 235-237

How to Cite: Wijesinghe, W., Jayananda, M. and Sonnadara, D., 2008. Performance evaluation of multipliers in reconfigurable hardware. Journal of the National Science Foundation of Sri Lanka, 36(3), pp.235–237. DOI: http://doi.org/10.4038/jnsfsr.v36i3.160
Published on 29 Sep 2008.
Peer Reviewed

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