Design of fault-tolerant reversible Vedic multiplier in quantum cellular automata

This article is published under the Creative Commons CC-BY-ND License (http://creativecommons.org/licenses/by-nd/4.0/). This license permits use, distribution and reproduction, commercial and non-commercial, provided that the original work is properly cited and is not changed in anyway. Abstract: In modern computational technologies, a major challenge is the design of devices with smaller size, low power dissipation, and high speed. In order to achieve better optimisation in power dissipation, size and speed, it is necessary to find a technological change. Researchers are trying to find ways and means by introducing many architectural and behavioural changes in the available technologies. One such possible solution is to design digital circuits based on reversible logic and implement them in quantum cellular automata (QCA). In a multiplication process, partial product generation and the addition of partial products are the major factors contributing to the propagation delay. In this paper, Urdhwa Triyakbhyambased Vedic multiplier using reversible logic is proposed. Vedic multipliers result in faster partial products with less number of steps. Ripple carry adders are used for adding the partial product results to obtain the final product. The multiplier modules are constructed using fault-tolerant reversible KMD gates and hence, the proposed multiplier is a fault-tolerant Vedic multiplier. The designed multiplier is realised in QCA. In the proposed reversible Vedic multiplier, quantum cost is reduced up to 72 %, garbage output is reduced up to 87 %, constant input is reduced up to 87 % and the number of gates are reduced up to 57 % compared to the existing conventional and Vedic multipliers.


INTRODUCTION
In computing, every computing system needs to be optimised in power dissipation, area and speed to be efficient. It is very difficult to achieve all three parameters in a single step with the currently available Complementary Metal Oxide Semiconductor (CMOS) technologies. Moreover, scaling of CMOS limits its performances in many dimensions such as current leakage, noise, interconnections, etc. Hence, it is desirable to move on to other technologies to achieve computational efficiency. Reversible logic-based computation is a better alternative to move towards effective computing systems.
In 1961, Launder invented that losing a bit of information causes heat in the order of kTln2 Joules (where, k -Boltzmann's constant and T -absolute temperature) (Landauer, 1961). This heat is generated due to the bit loss in conventional computation. In 1973, Bennett proposed the reversible logic-based computation, which has a one-to-one unique mapping between the input and output (Bennett, 1973) i.e. the number of inputs and outputs are same. Hence, the kTln2 Joules of heat dissipation is avoided.
Fault detection and avoidance are major problems in digital circuits and it could be achieved by designing a fault-tolerant circuit. Fault-tolerance could be achieved by parity preservation, which means to have an equal parity in inputs and outputs; i.e., exclusive OR gate (XOR) of all the inputs and outputs must be equal (Behrooz, 2006). Therefore, for a reversible logic circuit to be fault-tolerant, it should have parity preservation.

December 2019
Journal of the National Science Foundation of Sri Lanka 47(4) In a computing system, one of the complicated and time-consuming computations is multiplication. Many researchers have proposed different methods for multiplication in order to speed up the computation of the multiplier. Some of the currently available multipliers are designed with carry-save adder (CSA), carry-select adder and carry-skip adders for fast product generation. Later, special multipliers such as Baugh Wooley multiplier, Wallace multiplier, serial / parallel multiplier and Booth multipliers (Hamacher et al., 2011) have been introduced to speed up the process. However, neither the complexity nor the critical path delay in the multiplication process is reduced.
A better alternative solution is Vedic multiplication, which is an ancient way of performing multiplication. Vedic mathematics is reinvented by Sri Bharati Krisna Tirtha from the Indian Veda scriptures. It has 16 sutras and out of them Nikhilam Sutram, Urdhva Tiryakbhayam, and Anurupye are the most popularly used sutras. The advantage of the Vedic multiplier is that it has very simple procedures for complex multiplication . The multiplication could be extended to n-bits with some minor modifications.
A n×n reversible Vedic multiplier is proposed and implemented in field-programmable gate array (FPGA) and its resource utilisation is discussed in Poornima et al. (2013). A reversible logic-based Urdhva Tiryakbhyam multiplication algorithm is implemented in FPGA. Peres, BME and Toffoli gates are utilised to construct the reversible 4×4 Vedic multiplier (Shivarathnamma et al., 2016). In Srikanth et al. (2014) a 32-bit reversible Vedic multiplier based on Urdhva Tiryakbhayam sutra is designed with Peres, HNG and Feynman gate. Here also, Verilog HDL-based design was implemented in FPGA and the delay and power dissipation were analysed.
A 4-bit reversible Vedic multiplication is implemented in FPGA. The multiplier is constructed with Peres, Feynman and NFT gates, in which NFT is a fault-tolerant gate . In this paper, reversible logic performance measures (quantum cost, constant input, garbage outputs) are considered. In Haghparast et al. (2009), MKG and HNG reversible gates are introduced for the optimisation in reversible multiplication. The partial product generation is completed with the Peres, HNG gates. More significantly, hardware complexity of the multiplier is measured using logical calculation and a quantum circuit of the gates are introduced.
More recently, a new type of parity preserving gates was analysed (Valinataj, 2017). Here parity preserving gates, double Feynman, Fredkin, NFT, MIG, double Peres and ZPLG (5×5) are discussed. These gates are otherwise named as conservative gates or fault-tolerant gates. A signed multiplier is constructed using these fault-tolerant gates but the multiplier works based on the conventional array multiplication. Thus, its number of gates increases, thereby its hardware complexity is also a little high (Valinataj, 2017).
A detailed procedure to conduct the Urdhva Tiryagbhyam Sutra-based Vedic multiplication is explained by (Subramanian et al., 2016). An 8-bit multiplier is designed with conventionally available reversible gates such as Peres and Feynman gates. This multiplier acts as a part of the arithmetic logic unit. Further, their performance measures are done using reversible logic parameters (Subramanian et al., 2016). The Vedic multiplication costs lower than the booth multiplication.
In Poornima et al., (2013), Shivarathnamma et al., (2016), Srikanth and Nasam (2016) and Saligram and Rakshith (2013), the final implementation is carried out on FPGA. Since it is a transistor-based approach, low power cosumption and reversibility cannot be assured. The reversible Vedic multiplier were constructed by , Haghparast (2009) andSubramanian et al. (2016) but they are not fault-tolerant. The faulttolerant gate was used only by Valinataj (2017), for designing conventional multiplier. Till now, no multiplier was constructed with fault tolerance, reversibility, and realisation in QCA. Hence, the proposed fault-tolerant reversible Vedic multiplier in QCA is very important.
The paper first describes the currently available reversible gates and reviews multipliers. Then it explains the reversible logic metrics and QCA and illustrates the proposed reversible KMD gates and its quantum realisation. Thereafter, the steps of Vedic multiplication process and its QCA realisations are explained. Finally, it compares the conventional multipliers and existing Vedic multipliers with the proposed fault-tolerant reversible Vedic multiplier and concludes the paper stating the usefulness of Urdhva Tiryakbhayam multiplier.

Reversible logic metrics and QCA
A reversible gate is expected to have a distinctive mapping between its inputs and outputs; i.e., bijective. It is known as reversibility. In addition, if a reversible gate is capable of generating NOT, AND/NAND & OR/ Journal of the National Science Foundation of Sri Lanka 47 (4) December 2019 NOR functions, it is said to be a universal reversible gate (Kalyan, 2014).
The XOR function of inputs and outputs of the reversible gate has to be equal to a fault-tolerant reversible gate [11]. It is otherwise named as parity preservation or conservative logic. Considering I i 's are inputs and O i 's are outputs of a reversible gate, then it should satisfy the following equation (1), ally, a reversible gate is expected to have a distinctive mapping between its inputs and ts; ie., bijective. It is known as Reversibility. In addition, if a reversible gate is capable nerating NOT, AND/NAND & OR/NOR functions then it is said to be a Universal ible gate [Kalyan, 2014].
The XOR function of inputs and outputs of the reversible gate has to be equal with a tolerant reversible gate [11]. It is otherwise named as parity preservation or It is the number of 1×1 and 2×2 primitive gates used to realize the desired reversible function [Valinataj, 2017].
ge output: The number of outputs not utilized for promote computation is known as Garbage t. It is mainly used to maintain the reversibility [Poornima, 2013].

ant input:
It is defined as a stable value (either logical '0' or '1') set in the input of the reversible roughout the computation to derive the desired logical output [Poornima, 2013].

Logical calculation:
It is a measure of the number of XOR (α), AND (β) and NOT (δ) gate functions atory to obtain the reversible logic circuit [Haghparast, 2009].
The realization of the reversible circuit is performed in Quantum Cellular Automata ). It is a quantum cell consisting of four number of quantum dots. The position of the ons defines the logical state of the cell (either logic '0' or '1'). The electrons always y diagonally opposite positions as shown in Fig.1 (a, b). Reversible logic measures slightly deviate from conventional measure metrics. The commonly used reversible logic metrics are quantum cost, garbage output, constant input, and logical calculations.
These metrics are defined as follows,

Quantum cost:
It is the number of 1×1 and 2×2 primitive gates used to realise the desired reversible logic function (Valinataj, 2017).

Garbage output:
The number of outputs not utilised to promote computation is known as garbage output. It is mainly used to maintain the reversibility (Poornima et al., 2013).

Constant input:
It is defined as a stable value (either logical '0' or '1') set in the input of the reversible gate throughout the computation to derive the desired logical output (Poornima et al., 2013).

Logical calculation:
It is a measure of the number of XOR (α), AND (β) and NOT (δ) gate functions mandatory to obtain the reversible logic circuit (Haghparast et al., 2009).
The realisation of the reversible circuit is performed in quantum cellular automata (QCA). It is a quantum cell consisting of four quantum dots. The position of the electrons defines the logical state of the cell (either logic '0' or '1'). The electrons always occupy diagonally opposite positions as shown in Figure 1 (a, b).
The dimension of the quantum cell is in the order of nanometers. The quantum cellular automata have two major advantages. They are, i. The computation and information flow (signal propagation) take place simultaneously. It makes the computation and communication faster in QCA.
ii. Each quantum cell is behaving as a computation unit as well as an interconnection line. Therefore, no separate interconnection lines are required. Because of these two advantages, QCA-based implementation of fault-tolerant reversible logic circuits provides efficiency in power consumption, area, and speed of computation (Sridharan & Pudi, 2015).

Proposed reversible KMD gates and its QCA realisation
Many researchers are proposing new reversible gates when there is a need to design reversible circuits at an optimum cost. It would be done by either proposing a novel reversible gate or using the combination of available reversible gates configuration. Some of the proposed reversible gates are BME (Shivarathnamma et al., 2016), MRG, DKG (Biswas et al., 2014), NFT Ali et al., 2015), TSG, MKG, HNG (Haghparast et al., 2009), MIG and ZPLG (Valinataj, 2017). These gates mostly satisfy reversibility and universality, but they rarely have the property of fault-tolerance. The characteristics of the proposed and existing reversible gates are shown in Table 1.
In this paper, four fault-tolerant reversible KMD gates are proposed. These gates have reversibility, universality, and fault-tolerance (parity preservation) properties (Kamaraj & Marichamy, 2018). The configuration of KMD gates are depicted in Figure 2 (a, b, c, d). ii.
Each quantum cell is behaving as a computation un interconnection line. So, there is no separate intercon required.
Because of these two advantages, QCA based implementation Reversible logic circuits provides efficiency in power consumption, a computation [Sridharan et al., 2015].  [Haghparast et al., 2009], MIG, and ZPLG [Valinataj, 2017]. satisfy reversibility and universality, but they rarely have the property of F characteristics of the proposed and existing reversible gates are shown in T ii.
Each quantum cell is behaving as a computati interconnection line. So, there is no separate in required.
Because of these two advantages, QCA based impleme Reversible logic circuits provides efficiency in power consumpt computation [Sridharan et al., 2015].  Because of these two advantages, QCA based implementation of Reversible logic circuits provides efficiency in power consumption, area, computation [Sridharan et al., 2015].  [Haghparast et al., 2009], MIG, and ZPLG [Valinataj, 2017]. The satisfy reversibility and universality, but they rarely have the property of Fault characteristics of the proposed and existing reversible gates are shown in Table   Table 1: Reversibility, Universality and Fault Tolerance of Reversib The KMD gates need a minimum number of cells for its realisation in QCA compared to the previously proposed reversible gates. From Table 2, it is observed that KMD gates require a minimum number of cells for its realisation, and therefore the area occupied gets minimised. The QCA realisation and quantum structure of KMD gates are shown in Figures 3 and 4, respectively.

Vedic multiplier
The literal meaning of Urdhva Tiryagbhyam Sutra is 'Vertically and Crosswise'. It performs multiplication in vertical and crosswise and the partial products are  In this paper, four numbers of Fault-tolerant reversible KMD gates are proposed. These gates have reversibility, universality, and fault-tolerance (parity preservation) properties [Kamaraj et al., 2018a]. The configuration of KMD gates are depicted in Fig.2 (a-d).  ]. The configuration of KMD gates are depicted in Fig.2 (a-d).    1. The least significant bit of the two numbers is multiplied to form the LSB of the result (vertical). 2. The next higher bits are cross multiplied with each other and the results are added together to produce the next digit of multiplication. 3. The carry part of step 2 is added to the next level sum output to form the next higher bit. 4. All the bits are processed in the same way as in step 2 and step 3 until the last digit of the operand is reached. 5. Record the final product of the Vedic multiplication.

2×2 Vedic multiplier
A two bit multiplication of the two numbers A×B could be carried out in the following manner. The logical expression of the final product is,     The corresponding hardware architecture of the 2×2 Vedic multiplier is depicted in Fig.6a. It has logical AND gates and adders for calculating the product terms. Fault tolerant reversible KMD gates structure of the Vedic multiplier is shown in Fig.6b. In this structure all the functional modules are designed using KMD gates only.  The corresponding hardware architecture of the 2×2 Vedic multiplier is depicted in Fig.6a. It has logical AND gates and adders for calculating the product terms. Fault tolerant reversible KMD gates structure of the Vedic multiplier is shown in Fig.6b. In this structure all the functional modules are designed using KMD gates only. The corresponding hardware architecture of the 2×2 Vedic multiplier is depicted in Fig.6a. It has logical AND gates and adders for calculating the product terms. Fault tolerant reversible KMD gates structure of the Vedic multiplier is shown in Fig.6b. In this structure all the functional modules are designed using KMD gates only. The corresponding hardware architecture of the 2×2 Vedic multiplier is depicted in Fig.6a. It has logical AND gates and adders for calculating the product terms. Fault tolerant reversible KMD gates structure of the Vedic multiplier is shown in Fig.6b. In this structure all the functional modules are designed using KMD gates only. The corresponding hardware architecture of the 2×2 Vedic multiplier is depicted in Fig.6a. It has logical AND gates and adders for calculating the product terms. Fault tolerant reversible KMD gates structure of the Vedic multiplier is shown in Fig.6b. In this structure all the functional modules are designed using KMD gates only. The corresponding hardware architecture of the 2×2 Vedic multiplier is depicted in Fig.6a. It has logical AND gates and adders for calculating the product terms. Fault tolerant reversible KMD gates structure of the Vedic multiplier is shown in Fig.6b. In this structure all the functional modules are designed using KMD gates only. The corresponding hardware architecture of the 2×2 Vedic multiplier is depicted in Fig.6a. It has logical AND gates and adders for calculating the product terms. Fault tolerant reversible KMD gates structure of the Vedic multiplier is shown in Fig.6b. In this structure all the functional modules are designed using KMD gates only. The corresponding hardware architecture of the 2×2 Vedic multiplier is depicted in Fig.6a. It has logical AND gates and adders for calculating the product terms. Fault tolerant reversible KMD gates structure of the Vedic multiplier is shown in Fig.6b. In this structure all the functional modules are designed using KMD gates only. The corresponding hardware architecture of the 2×2 Vedic multiplier is depicted in Figure 6a. It has logical AND gates and adders for calculating the product terms. Fault tolerant reversible KMD gates structure of the Vedic multiplier is shown in Figure 6b. In this structure all the functional modules are designed using KMD gates only.
Journal of the National Science Foundation of Sri Lanka 47(4) December 2019

4×4 Vedic Multiplier
The 4-bit Vedic multiplier (VM) module is constructed using 2-bit Vedic multiplier unit (VMi) in four times, three 4-bit ripple carry adders & one half adder gate which are shown in the Fig.7. The inputs Ai (A3A2A1A0) and Bi (B3B2B1B0) are specified to 2-bit Vedic multiplier bitwise, and then the multiplier output is forwarded to the 4-bit RCA adder. The output from the RCA adder consists of 4-bit sum output and a 1-bit carry value. The half adder is used to sum the carry at the first two phases of ripple carry adder. The output of 4-bit multiplier consists of 8-bit product term (Pi -P7…P0) [Gowthami et al.,, 2018].
In a similar way, higher order Vedic multipliers are constructed with the 2-bit VMi as the base module and RCA adders for summation of the partial products. The n-bit Vedic multiplier uses four n/2-bit multipliers, one n-bit RCA adder, one n-bit Full adder, and one ((n/2)−1) bit RCA adder (using only Half adder). For example, construction of 16-bit Vedic multipliers by this comprehensive structure requires four 8-bit multiplier units, one 16-bit RCA adder, one 16-bit Full adder, and one 7-bit RCA adder (using only Half adder). So, using this general, n-bit Vedic multiplication unit construction is illustrated in Fig.8 [Kamaraj et al., 2018b].

Fault-tolerant reversible AND gate
By setting logic '1' in the third input of KMD gate 2, AND gate function is Remaining outputs are called as Garbage outputs (G). In that way, many logical funct be derived from the single gate. Fig.9 shows that schematic and QCA realization o gate using KMD gate 2.

4×4 Vedic multiplier
The 4-bit Vedic multiplier (VM) module is constructed using the 2-bit Vedic multiplier unit (VM i ) four times, three 4-bit ripple carry adders and one half adder gate, which are shown in Figure 7. The inputs A i (A 3 A 2 A 1 A 0 ) and B i (B 3 B 2 B 1 B 0 ) are specified to 2-bit Vedic multiplier bitwise, and then the multiplier output is forwarded to the 4-bit RCA adder. The output from the RCA adder consists of 4-bit sum output and a 1-bit carry value. The half adder is used to sum the carry at the first two phases of ripple carry adder. The output of 4-bit multiplier consists of 8-bit product term (P i -P 7 …P 0 ) (Gowthami & Satyanarayana, 2018).
In a similar way, higher order Vedic multipliers are constructed with the 2-bit VM i as the base module and RCA adders for summation of the partial products. The n-bit Vedic multiplier uses four n/2-bit multipliers, one n-bit RCA adder, one n-bit full adder, and one [(n/2)−1] bit RCA adder (using only half adder). For example, construction of 16-bit Vedic multipliers by this comprehensive structure requires four 8-bit multiplier units, one 16-bit RCA adder, one 16-bit full adder, and one 7-bit RCA adder (using only half adder). General n-bit Vedic multiplication unit construction using this is illustrated in Figure 8 (Kamaraj et al., 2018b).

QCA realisation of reversible Vedic multiplier
The necessary modules for designing a multiplier are AND gate, half adder, and a full adder. These functions could be derived from KMD gates. The reversible Vedic multiplier modules are designed with fault-tolerant reversible gates and it is called fault-tolerant reversible Vedic multiplier.

December 2019
Journal of the National Science Foundation of Sri Lanka 47(4) Fig.9. Fault-tolerant reversible AND Gate and QCA structure using KMD gate 2

Fault-Tolerant Reversible Vedic Multiplier
The fault-tolerant reversible Vedic multiplier is constructed by using three KMD gates. In this multiplier, the multiplication process includes only six steps. The addition process is computed by using KMD gates. Here the KMD gate 2, KMD gate 3 and KMD gate 4 are used to generate the AND function, half adder and full adder respectively. The fault tolerant reversible Vedic multiplier using KMD gates and its corresponding QCA structure is given in

Fault-Tolerant Reversible Vedic Multiplier
The fault-tolerant reversible Vedic multiplier is constructed by using three KMD gates. In this multiplier, the multiplication process includes only six steps. The addition process is computed by using KMD gates. Here the KMD gate 2, KMD gate 3 and KMD gate 4 are used to generate the AND function, half adder and full adder respectively. The fault tolerant reversible Vedic multiplier using KMD gates and its corresponding QCA structure is given in

Fault-tolerant reversible AND gate
By setting logic '1' in the third input of KMD gate 2, AND gate function is derived. The remaining outputs are called garbage outputs (G). In that way, many logical functions can be derived from the single gate. Figure 9 shows the schematic diagram and QCA realisation of AND gate using KMD gate 2.
Journal of the National Science Foundation of Sri Lanka 47(4) December 2019

Fault-tolerant reversible half adder
By setting logic '0' in the third input of KMD gate 3 and fourth input as a second input (B), the half adder can be obtained. The remaining outputs are called garbage outputs (G). Figure 10 shows the schematic diagram of half adder using KMD gate 3 and its QCA realisation.

Fault-tolerant reversible full adder
Constant input logic '0' set at fourth and fifth input of KMD gate 4, would make it a full adder. The remaining outputs are called garbage outputs (G). Figure 11 shows the schematic diagram of full adder using KMD gate 4 and its QCA realisation.

Fault-tolerant reversible Vedic multiplier
The fault-tolerant reversible Vedic multiplier is constructed using three KMD gates. In this multiplier, the multiplication process includes only six steps. The addition process is computed by using KMD gates. Here KMD gates 2, 3 and 4 are used to generate the AND function, half adder and full adder, respectively. The fault tolerant reversible Vedic multiplier using KMD gates and its corresponding QCA structure is given in Figures 12 and 13, respectively.

RESULTS AND DISCUSSION
The 4-bit Vedic multiplier depicted in Figure 7 has been constructed using Fault-tolerant reversible KMD gates as shown in Figure 12. The corresponding QCA architecture is designed in QCA designer 2.0.3. Fault-tolerance of the Vedic multiplier has been achieved in two ways: (i) designing it fully with Fault-tolerant KMD gates and (ii) constructing with a combination of fault-tolerant KMD and conventional reversible gates (Fredkin, Toffoli). In both of these approaches, the Vedic multiplier is a faulttolerant reversible multiplier.
The 2×2 Vedic multiplier has AND gate and half adders as described in the previous section. The total cost for construction in approach 1 is 110. Similarly, the higher order multipliers are constructed from the lower order multipliers. The cost calculation of individual modules of the multiplier and the total costs are listed in Table 3. The total cost includes the sum of quantum cost, garbage output, constant inputs and the number of gates.
In approach 2, the AND gate is constructed using a Fredkin gate instead of KMD gates. However, it is a faulttolerant reversible multiplier. The cost calculation of individual units and the total costs are shown in Table 4.     The designed fault-tolerant reversible Vedic multiplier cost performance was compared with the existing conventional and reversible Vedic multipliers and they are shown in Table 5. The performance of the proposed method shows an improvement compared to the existing multipliers in terms of quantum cost, garbage output, constant input, and logical calculations. The percentage of improvement is shown in Table 6 with respect to the existing multitpliers.

CONCLUSION
In general, computation speed of a system is based on the hardware architecture and the data path design. In this paper, an Urdhwa Triyakbhyam-based Vedic multiplier has been designed in reversible logic. Vedic multipliers perform computations in minimum number of steps and therefore faster. The necessary functional modules are AND logic, half adder and full adder. These functional modules are constructed in two different approaches.
In the first approach all the functional modules are constructed using fault tolerant reversible KMD gates only, and in the second approach combination of Fredkin and KMD gates are used. The functional simulation is performed in QCA environment using QCADesigner 2.0.3. The performance measure shows that the proposed fault-tolerant reversible Vedic multiplier has improved in quantum cost (14 -72 %), garbage output (57 -80 %), constant input (78 -87 %), and a number of gates (50 -62 %) compared to the existing design. Further, its logical calculation or hardware complexity is 13α+11β+6γ, which is comparable with the existing design. Thus, it is concluded that the computation speed and efficiency can be improved by crosswise and vertical multiplication for the proposed fault-tolerant reversible Vedic multiplier.